SLVS-EC v3.0 Rx IP

Overview

SLVS-EC v3.0 Rx IP is an interface IP core that runs on Altera® FPGAs. Using this IP, you can quickly and easily implement products that support the latest SLVS-EC standard v3.0. You will also receive an "Evaluation kit" for early adoption.

  • Altera® FPGAs can receive signals directly from the SLVS-EC Interface.
  • Compatible with the latest SLVS-EC Specification Version 3.0.
  • Supports powerful De-Skew function. Enables board design without considering Skew that occurs between lanes.
  • "Evaluation kit”(see below) is available for speedy evaluation at the actual device level.

Example of system configuration using this IP
Example of system configuration using this IP

Overview of SLVS-EC Standard

  • SLVS-EC (Scalable Low Voltage Signaling with Embedded Clock) is an interface standard for high-speed & high-resolution image sensors developed by Sony Semiconductor Solutions Corporation.
  • The SLVS-EC standard is standardized by JIIA (Japan Industrial Imaging Association).

SLVS-EC Connection with Sensor
SLVS-EC Connection with Sensor

Features

  • SLVS-EC Specification Version 1.2/2.0 and the latest 3.0 are supported.
  • Provides various functions defined in the SLVS-EC Link Layer.
    • Selectable 32 or 64 pixel for output interface
    • Supports 8, 10, 12, 14, 16 bit/pixel
  • Realizes transfer with less overhead compared to conventional ANSI 8b10b by taking advantage of GCC (Gigabit Channel Coding) features added in the latest SLVS-EC Version 3.0.
  • Supports error correction using Error Correction Code (ECC)
  • Supports Byte to Pixel conversion in 1, 2, 4, 6, and 8 lane configurations.
  • Header analysis and payload error detection.
  • Compile options allow removal of unnecessary functions.

Specifications

Specifications

*1: Fixed by compiler option
*2: Limited support for Option 2

Scheduled IP release date (by supported FPGA)

Altera® FPGA
  • Arria® 10 FPGA : Scheduled for release in July 2024
  • Agilex™ 7 FPGA : Scheduled for release in July 2024
  • Agilex™ 5 FPGA : Scheduled for release in 2024
    • For details of our SLVS-EC v3.0 Rx IP for Agilex™ 5 FPGA, please contact us.

Evaluation Kit:  Luminous

Luminous Card & Sensor
Luminous Card & Sensor

Orders are scheduled to be received in the summer of 2024
* Please contact us for availability details.

Using Evaluation Kit

Connection image
Connection image
External Appearance
External Appearance

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